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mos integrated circuit m pd75p116 4-bit single-chip microcomputer data sheet ? nec corporation 1994 document no. ic-3358 (o. d. no. ic-7599a) date published february 1994 p printed in japan the mark h shows major revised points. description the m pd75p116 is a version of the m pd75116 in which the on-chip mask rom is replaced by one-time prom which can be written to once only. since the m pd75p116 is capable of program write by a user, it is suitable for evaluation in system develop- ment and limited production. detailed functional descriptions are shown in the following users manual. be sure to read for design purposes. m pd751 series users manual : iem-922 features ? m pd75116 compatible ? program memory (prom) capacitance : 16256 8 bits ? data memory (ram) capacitance : 512 4 bits ? single power supply 5 v 10% the information in this document is subject to change without notice. ordering information ordering code package quality grade m pd75p116cw 64-pin plastic shrink dip (750 mil) standard m pd75p116gf-3be 64-pin plastic qfp (14 20 mm) standard please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. note there are no on-chip pull-up resistor and power-on reset function by means of a mask option. h
2 m pd75p116 pin configuration (top view) 64-pin plastic shrink dip (750 mil) 1 p13/int3 2 p12/int2 3 p11/int1 4 p10/int0 5 pth03 6 pth02 7 pth01 8 pth00 9 ti0 10 ti1 11 p23 12 p22/pcl 13 p21/pto1 14 p20/pto0 15 p03/si 16 p02/so 17 p01/sck 18 p00/int4 19 p123 20 p122 21 p121 22 p120 23 p133 24 p132 25 p131 26 p130 27 p143 28 p142 29 p141 30 p140 31 v pp 32 v dd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss p90 p91 p92 p93 p80 p81 p82 p83 p70 p71 p72 p73 p60 p61 p62 p63 x1 x2 reset p50 p51 p52 p53 p40 p41 p42 p43 p30/md0 p31/md1 p32/md2 p33/md3 m pd75p116cw
3 m pd75p116 64-pin plastic qfp (14 20 mm) m sck : serial clock so : serial output si : serial input pto0, pto1 : programmable timer output pcl : clock output pth00 to pth03 : programmable threshold input int0, int1, int4 : external vectored interrupt input int2, int3 : external test input ti0, ti1 : timer input x1, x2 : clock oscillation reset : reset nc : no connection v dd : positive power supply v ss : ground v pp : programming power supply md0 to md3 : mode selection pin name p00 to p03 : port 0 p10 to p13 : port 1 p20 to p23 : port 2 p30 to p33 : port 3 p40 to p43 : port 4 p50 to p53 : port 5 p60 to p63 : port 6 p70 to p73 : port 7 p80 to p83 : port 8 p90 to p93 : port 9 p120 to p123 : port 12 p130 to p133 : port 13 p140 to p143 : port 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 20 21 22 23 24 25 26 27 28 29 30 31 32 p81 p80 p93 p92 p91 p90 v ss p13/int3 p12/int2 p11/int1 p10/int0 pth03 pth02 64 63 62 61 60 59 58 57 56 55 54 53 52 p42 p43 p30/md0 p31/md1 p32/md2 v pp p140 p141 p142 p143 p130 x2 x1 p41 p40 p53 p52 p51 p50 reset p63 p62 p61 p60 p73 p72 p71 p70 p83 p82 17 18 19 p131 p132 p133 p120 p121 p122 p123 p00/int4 p01/sck p02/so p03/si p20/pto0 p21/pto1 p22/pcl p23 t11 t10 pth00 pth01 35 34 33 v dd p33/md3 m pd75p116gf-3be
4 m pd75p116 overview of functions rom ram description 43 0.95 m s, 1.91 m s, 15.3 m s (4.19 mhz operation) 3-stage switching capability 16256 8 512 4 4 bits 8 4 banks (memory mapping) 3 types of accumulators corresponding to bit length of manipulated data ? 1-bit accumulator (cy), 4-bit accumulator (a), 8-bit accumulator (xa) total 58 ? cmos input pins : 10 ? cmos input/output pins (led direct drive capability) : 32 ? middle-high voltage n-ch open-drain input/output pins (led direct drive capability) : 12 ? comparator input pins (4-bit precision) : 4 ? 8-bit timer/event counter 2 ? 8-bit basic interval timer (watchdog timer applicable) ? 8 bits ? lsb-first/msb-first switchable ? two transfer modes (transmit-receive/receive-only mode) external : 3, internal : 4 external : 2 ? stop/halt mode ? various bit manipulation instructions (set, reset, test, boolean operation) ? 8-bit data transfer, comparison, operation, increment/decrement instructions ? 1-byte relative branch instruction ? geti instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte C40 to +85 c 5 v 10 % ? bit manipulation memory (bit sequential buffer : 16 bits) on-chip ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20mm) item basic instructions minimum instruction execution time internal memory general register accumulator input/output port timer/counter serial interface vectored interrupt test input standby instruction set operating temperature range operating voltage others package
5 m pd75p116 p ort 0 port 1 4 4 p00-p03 p10-p13 port 3 port 4 port 5 port 6 4 4 4 4 port 2 4 p20-p23 p30-p33 /md0-md3 p40-p43 p50-p53 p60-p63 port 7 4 p70-p73 sp(8) bank general reg. ram data memory 512 4 bits decode and control cy alu program counter (14) prom program memory 16256 8 bits reset v ss stand by control v dd cpu clock clock generator clock divider clock output control x2 x1 pcl/p22 f x / 2 n basic interval timer inter- rupt control intt1 intbt port 14 4 p140-p143 port 12 4 p120-p123 timer/event counter intt0 ti0 pto0/p20 timer/event counter ti1 pto1/p21 serial interface intsio sck/p01 so/p02 si/p03 program- mable threshold port #0 pth00-pth03 int4/p00 int2/p12 int1/p11 int0/p10 int3/p13 port 13 4 p130-p133 port 9 4 p90-p93 port 8 4 p80-p83 bit seq. buffer (16) 4 #0 #1 v pp f block diagram
6 m pd75p116 contents 1. pin functions .................................................................................................................................... 7 1.1 port pins ..................................................................................................................................................... 7 1.2 other pins ................................................................................................................................................... 8 1.3 pin input/output circuits ................................................................................................................... 9 1.4 recommended connection of m pd75p116 unused pins ........................................................... 10 1.5 notes on using p00/int4 pin and reset pin .................................................................................. 10 2. differences between m pd75p116 and m pd75116 ...................................................................... 11 3. prom (program memory) write and verify .......................................................................... 12 3.1 program memory write/verify operating modes ................................................................... 12 3.2 program memory write procedure ................................................................................................ 13 3.3 program memory read procedure ................................................................................................. 14 4. electrical specifications ............................................................................................................ 15 5. package information .................................................................................................................... 26 6. recommended soldering conditions ..................................................................................... 28 appendix a. development tools ...................................................................................................... 29 appendix b. related documentation ............................................................................................ 30
7 m pd75p116 function 4-bit input port (port 0). 4-bit input port (port 1). 4-bit input/output port (port 2). programmable 4-bit input/output port (port 3). input/output can be specified bit-wise. 4-bit input/output port (port 4). data input/output pin for program memory (prom) write/verify (low-order 4 bits). 4-bit input/output port (port 5). data input/output pin for program memory (prom) write/verify (high-order 4 bits). programmable 4-bit input/output port (port 6). input/output can be specified bit-wise. 4-bit input/output port (port 7). 4-bit input/output port (port 8). 4-bit input/output port (port 9). n-ch open-drain 4-bit input/output port (port 12). +12 v withstand voltage. n-ch open-drain 4-bit input/output port (port 13). +12 v withstand voltage. n-ch open-drain 4-bit input/output port (port 14). +12 v withstand voltage. 1. pin functions 1.1 port pins dual- function pin int4 sck so si int0 int1 int2 int3 pto0 pto1 pcl md0 to md3 i/o circuit type *1 b f e b b e e e e e e e e m-a m-a m-a *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *1. indicates schmitt-triggered input. 2 . led direct drive capability input/output input input/output input/output input input input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120-p123 p130-p133 p140-p143 8-bit i/o after reset input input input input input input input input input input input input input
8 m pd75p116 1.2 other pins dual- function pin p20 p21 p01 p02 p03 p00 p10 p11 p12 p13 p22 p30 to p33 i/o circuit type *1 n b e f e b b b b e b e pin name pth00 to pth03 ti0 ti1 pto0 pto1 sck so si int4 int0 int1 int2 int3 pcl x1, x2 reset md0 to md3 v dd v ss v pp *2 input/output input input input/output input/output input/output input input input input input/output input input/output function variable threshold voltage 4-bit analog input port. external event pulse input to timer/event counter. or edge detection vectored interrupt input pin, or 1-bit input is also possible. timer/event counter output pin. serial clock input/output pin. serial data output pin. serial data input pin. edge detection vector interrupt input pin (detection of both rising and falling edges). edge detection vector interrupt input pin (detection edge selectable). edge detection testable input pin (rising edge detection) clock output pin system clock oscillation crystal/ceramic connection pin. when an external clock is used, the clock is input to x1 and the inverted clock is input to x2. system reset input pin (low-level active). mode selection pin for program memory (prom) write/ verify. positive power supply pin. applies +6 v for write/verify. gnd potential pin. program voltage impression pin for program memory (prom) write/verify. connected to v dd directly in normal operation. applies +12.5 v for prom write/verify. after reset input input input input input input *1. indicates schmitt-triggered input. 2. the device will not operate correctly unless v pp is connected to v dd directly in normal use.
9 m pd75p116 1.3 pin input/output circuits the input/output circuits of each pin of the m pd75p116 are shown by in abbreviated form. p-ch v dd in n-ch in p-ch v dd out n-ch data output disable in/out data output disable type d type a in/out data output disable type d in/out n-ch (+12 v withstand voltage) data output disable middle-high voltage input buffer (+12 v withstand voltage) in comparator v ref (threshold voltage) + ? type a type b input/output circuit made up to a type d push-pull output and type b schmitt-triggered input. schmitt-triggered input with hysteresis characteristic type d push-pull output with high impedance output capability (p-ch and n-ch both off) type e this is an input/output circuit made up of a type d push-pull output and type a input buffer. type f type m-a type n cmos specification input buffer type b
10 m pd75p116 1.4 recommended connection of m pd75p116 unused pins pin pth00 to pth03 ti0 ti1 p00 p01 to p03 p10 to p13 p20 to p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 recommended connection connect to v ss or v dd . connect to v ss . connect to v ss or v dd . connect to v ss . input status : connect to v ss or v dd . output status : leave open. v dd v dd p00/int4, reset 1.5 notes on using p00/int4 pin and reset pin the p00/int4 and reset pins have a test mode setting function (for ic test) which tests internal operations of pin of the m pd75p116 in addition to those functions given in 1.1 and 1.2. the test mode is set when voltage greater than v dd is applied to either pin. therefore, even during normal operation, the test mode is engaged when noise greater than v dd is added, thus causing interference with normal operation. for example, this problem may occur if the p00/int4 and reset pins wiring is too long, causing line noise. to avoid this, try to suppress line noise in wiring. if line noise is still high, try elimminating the noise using the exterior add-on components shown in the figures below. l l connect a diode with low v f (0.3 v max.) between the v dd and the pin. l l connect a capacitor between the v dd and the pin. v dd v dd p00/int4, reset diode with low v f
11 m pd75p116 2. differences between m pd75p116 and m pd75116 the m pd75p116 is a product in which the program memory (mask rom) of the m pd75116 is changed to a user programmable prom. other functions of the m pd75p116 and m pd75116 are virtually the same only with the differences shown in table 2-1. for details of cpu functions and on-chip hardware, see the m pd75116 users manual (iem-922) . table 2-1 differences between m pd75p116 and m pd75116 item m pd75p116 m pd75116 program memory one-time prom mask rom 0000h-3f7fh (16256 8 bits) data memory 0000h-01ffh (512 4 bits) pull-up resistor (ports 12 to 14) no mask option power-on reset function operating voltage range 5 v 10 % 2.7 to 6.0 v 31 pins (sdip) v pp nc pin function 57 pins (qfp) 33 to 36 pins (sdip) p33/md3 to p30/md0 p33 to p30 59 to 62 pins (qfp) electrical specification different consumption current, operating temperature range, etc. refer to the electrical specifications parameters for each data sheet for details. other different noise resistance, noise radiation, etc., due to difference in the size of circuits and mask layout. note the prom and rom products differ in noise resistance and noise radiation. if you are considering replacement of the prom products by the mask rom product in the transition from preproduction to volume production, this should be thoroughly evaluated with the mask rom cs product (not es product). h
12 m pd75p116 function voltage application pin for program memory write/verify (normally v dd potential). address update clock inputs for program memory write/ verify. inverse of x1 pin signal is input to x2 pin. operating mode selection pin for program memory write/ verify. 8-bit data input/output pins for progrm memory write/ verify. supply voltage application pin. applies 5 v 10 % in normal operation, and 6 v for program memory write/verify. pin name v pp x1, x2 md0 to md3 p40 to p43 (low-order 4 bits) p50 to p53 (high-order 4 bits) v dd note since the m pd75p116 is a one-time prom version, uv-ray erasure is not possible. 3.1 program memory write/verify operating modes the m pd75p116 assumes the program memory write/verify mode is +6 v and +12.5 v are applied respec- tively to the v dd and v pp pins. the table below shows the operating modes available by the md0 to md3 pin setting in this mode. the rest of pins are all set at the v ss potential by the pull-down resistor. v pp +12.5 v v dd +6 v md0 h l l h md1 l h l md2 h h h h md3 l h h h operating mode program memory address zero-clear write mode verify mode program inhibit mode operating mode setting : l or h 3. prom (program memory) write and verify the rom built into the m pd75p116 is a 16256 8-bit prom. the pins shown in the table below are used to write/verify this prom. there is no address input; instead, a method to update the address by the clock input from the x1 pin is adopted.
13 m pd75p116 data input data input write verify additional write address increment repeated x times data output v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 3.2 program memory write procedure the program memory writing procedure is shown below. high-speed write is possible. (1) pull down a pin which is not used to v ss via the resistor. a low-level signal is input to the x1 pin. (2) supply +5 v to the v dd and v pp pins. (3) 10 m s wait. (4) the program memory address 0 clear mode. (5) supply +6 v and +12.5 v respectively to v dd and v pp . (6) the program inhibit mode. (7) write data in the 1-ms write mode. (8) the program inhibit mode. (9) the verify mode. if written, proceed to (10); if not written, repeat (7) to (9). (10) (number of times written in (7) to (9): x) 1-ms additional write. (11) the program inhibit mode. (12) update (+1) the program memory address by inputting 4 pulses to the x1 pin. (13) repeat (7) to (12) up to the last address. (14) the program memory address 0 clear mode. (15) change the v dd and v pp pins voltage to +5 v. (16) power off. the diagram below shows the procedure of the above (2) to (12).
14 m pd75p116 data output data output v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 ?? 3.3 program memory read procedure the m pd75p116 can read the content of the program memory in the following procedure. (1) pull down a pin which is not used to v ss via the resistor. a low-level signal is input to the x1 pin. (2) supply +5 v to the v dd and v pp pins. (3) 10 m s wait. (4) the program memory address 0 clear mode. (5) supply +6 v and +12.5 v respectively to v dd and v pp . (6) the program inhibit mode. (7) the verify mode. if clock pulses are input to the x1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) the program inhibit mode. (9) the program memory address 0 clear mode. (10) change the v dd and v pp pins voltage to +5 v. (11) power off. the diagram below shows the procedure of the above (2) to (9).
15 m pd75p116 4. electrical specifications absolute maximum ratings (ta = 25 c) symbol test conditions rating unit v dd C0.3 to + 7.0 v v pp C0.3 to 13.5 v v i1 except ports 12 to 14 C0.3 to v dd + 0.3 v v i2 ports 12 to 14 C0.3 to +13 v v o C0.3 to v dd + 0.3 v 1 pin C15 ma total pins C30 ma peak value 30 ma effective value 15 ma peak value 100 ma effective value 36 ma peak value 100 ma effective value 36 ma t opt C40 to +85 c t stg C65 to +125 c 1 pin ports 0, 2 to 4, 12 to 14 total ports 5 to 9 total i ol *2 i oh parameter supply voltage supply voltage input voltage output voltage output current high output current low operating temperature storage temperature * 1. the power supply impedance (pull-up resistor) should be 50 k w or more when the voltage exceeding 10 v applied to ports 12, 13 and 14. 2. effective value should be calculated as follows: [effective value] = [peak value] ? duty note product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. *1
16 m pd75p116 typ. 4.19 max. 5.0 4 5.0 10 5.0 250 unit mhz ms mhz ms mhz ns recommended circuit parameter oscillator frequency (f xx ) *1 oscillation stabilization time *2 oscillator frequency (f xx ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high/low level width (t xh , t xl ) test conditions v dd = after v dd reaches 4.5 v. after v dd reaches 4.5 v. min. 2.0 2.0 2.0 100 resonator ceramic resonator crystal resonator external clock *3 *3 * 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execu- tion time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. or stop mode release. 3. when the oscillator frequency is 4.19 mhz < f xx < C 5.0mhz, pcc = 0011 should not be selected as instruction execution time. if pcc = 0011 is selected, 1 machine cycle becomes less than 0.95 m s, with the result that the specified min value of 0.95 m s cannot be observed. note when the system clock oscillator is used, the following points should be noted concerning wiring in the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc. ? keep the wiring as short as possible. ? do not cross any other signal lines. ? keep away from lines in which a high fluctuating current flows. ? ensure that oscillator capacitor connection points are always at the same potential as v ss . do not ground in a ground pattern in which a high current flows. ? do not take a signal from the oscillator. oscillation circuit characteristics (ta = C40 to +85 c, v dd = 5 v 10 %) x1 x2 c2 c1 x1 x2 c2 c1 m pd74hcu04 x1 x2 *3 h h
17 m pd75p116 parameter symbol test conditions min. typ. max. unit v ih1 other than below 0.7v dd v dd v v ih2 ports 0 & 1, ti0 & 1, reset 0.8v dd v dd v v ih3 ports 12 to 14 0.7v dd 12 v v ih4 x1, x2 v dd C0.5 v dd v v il1 other than below 0 0.3v dd v v il2 ports 0 & 1, ti0 & 1, reset 0 0.2v dd v v il3 x1, x2 0 0.4 v output voltage high v oh i oh = C1 ma v dd C1.0 v i ol = 15 ma ports 0, 2, to 9 0.55 2.0 v output voltage low v ol i ol = 10 ma ports 12 to 14 0.35 2.0 v i ol = 1.6 ma 0.4 v i lih1 other than below 3 m a i lih2 x1, x2 20 m a i lih3 v in = 12 v ports 12 to 14 20 m a i lil1 except x1 & x2 C3 m a i lil2 x1, x2 C20 m a i loh1 v out = v dd other than below 3 m a i loh2 v out = 12 v ports 12 to 14 20 m a i lol v out = 0 v C3 m a i dd1 v dd = 5 v 5 % *2 510ma i dd2 v dd = 5 v 5 % 500 1500 m a i dd3 stop mode, v dd = 5 v 5 % 0.5 20 m a input voltage high input voltage low input leakage current high input leakage current low output leakage current high output leakage current low power supply current *1 dc characteristics (ta = C40 to +85 c, v dd = 5 v 10 %) v in = v dd v in = 0 v *1. not including current flowing in comparator. 2. when processor clock control register (pcc) is set to 0011 operating in high-speed mode. 3. when pcc is set to 0100 and cpu is halted in halt mode. 4.19 mhz crystal oscillation c1 = c2 = 22 pf halt mode *3
18 m pd75p116 capacitance (ta = 25 c, v dd = 0 v) test conditions parameter input capacitance output capacitance i/o capacitance symbol c in c out c io unit pf pf pf comparator characteristics (ta = C40 to +85 c, v dd = 5 v 10 %) min. typ. max. 15 15 15 min. 0 0 typ. 1 max. 100 v dd v dd unit mv v v ma test conditions pthm7 set to "1" parameter comparison accuracy threshold voltage pth input voltage comparator circuit current consumption symbol v acomp v th v ipth f = 1 mhz unmeasured pins returned to 0 v.
19 m pd75p116 t cy vs. v dd cycle time t cy [ s] m supply voltage v dd [v] operating guaranteed range 10 5 5 1 0.5 0 1 2 3 4 5 6 symbol test conditions min. typ. max. unit v dd = 4.75 to 5.5 v 0.95 32 m s 1.1 32 m s f ti 0 1 mhz t tih , 0.48 m s t til t kcy input 0.8 m s output 0.95 m s t kh , intput 0.4 m s t kl output t kcy /2C50 ns t sik 100 ns t ksi 400 ns t kso 300 ns 5 m s t rsl 5 m s ac characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) t cy parameter cpu clock cycle time * (minimum instruction execution time = 1 ma- chine cycle) ti input frequency ti input high/low-level width sck cycle time sck high/low-level width si setup time (to sck - ) si hold time (from sck - ) so output delay time from sck int0 to int4 high/low- level width reset low level width t inth , t intl * the cycle time of the cpu clock ( f ) is determined by the oscillator frequency of the connected resonator and the processor clock control register (pcc). the graph on the below shows the cycle time t cy characteristics against supply voltage v dd . relation between cycle time and supply voltage note t cy vs. v dd characteristics are different from those of the m pd75p108
20 m pd75p116 ac timing test point (excluding ports 0 & 1, ti0, ti1, x1, x2, reset) clock timing ti input timing 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd test points t xl t xh 1/f x v dd - 0.5 0.4 x1 input t til t tih 1/f ti ti0, ti1 0.8 v dd 0.2 v dd
21 m pd75p116 serial transfer timing interrupt input timing reset input timing t kh sck t kl 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t sik t kcy t kso input data output data si so t ksi t intl t inth int0-int4 0.8 v dd 0.2 v dd t rsl reset 0.2 v dd
22 m pd75p116 stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel stop instruction execution v dd v dddr reset operating mode halt mode internal reset operation stop mode data retention mode t wait t srel data memory stop mode low supply voltage data retention characteristics (ta = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v data retention power supply current *1 i dddr v dddr = 2.0 v 0.1 10 m a release signal set time t srel 0 m s release by reset 2 17 /f x ms release by interrupt request *3 ms oscillation stabilization wait time *2 t wait *1. does not include current flowing in the comparator. 2. the oscillator stabilization wait time is the time during which cpu operation is halted to prevent unstable operation when oscillation begins. 3. depends on the setting of the basic interval timer mode register (btm) (table below). btm3 btm2 btm1 btm0 wait time (figure in parentheses is for f xx = 4.19 mhz) C000 2 20 /f xx (approx. 250 ms) C011 2 17 /f xx (approx. 31.3 ms) C101 2 15 /f xx (approx. 7.82 ms) C111 2 13 /f xx (approx. 1.95 ms) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal)
23 m pd75p116 dc programming characteristics (ta = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter input voltage high input voltage low input leakage current output voltage high output voltage low v dd supply current v pp supply current symbol v ih1 v ih2 v il1 v il2 i li v oh v ol i dd i pp unit v v v v m a v v ma ma max. v dd v dd 0.3 v dd 0.4 10 0.4 30 30 test conditions except x1 & x2 x1, x2 except x1 & x2 x1, x2 v in = v il or v ih i oh = C1 ma i ol = 1.6 ma md0 = v il , md1 = v ih typ. min. 0.7v dd v dd C0.5 0 0 v dd C1.0 note 1. ensure that v pp does not reach +13.5 v or above including overshot. 2. ensure that v dd is applied before v pp and cut off after v pp .
24 m pd75p116 ac programming characteristics (ta = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter address setup time *2 (to md0 ) md1 setup time (to md0 ) data setup time (to md0 ) address hold time *2 (from md0 - ) data hold time (from md0 - ) data output float delay time from md0 - v pp setup time (to md3 - ) v dd setup time (to md3 - ) initial program pulse width additional program pulse width md0 setup time (to md1 - ) data output delay time from md0 md1 hold time (from md0 - ) md1 recovery time (from md0 ) program counter reset time x1 input high-/low-level width x1 input frequency initial mode setting time md3 setup time (to md1 - ) md3 hold time (from md1 ) md3 setup time (to md0 ) data output delay time from address *2 data output hold time from address *2 md3 hold time (from md0 - ) data output float delay time from md3 unit m s m s m s m s m s ns m s m s ms ms m s m s m s m s m s m s mhz m s m s m s m s m s ns m s m s max. 130 1.05 21.0 1 4.19 130 typ. 1.0 min. 2 2 2 2 2 0 2 2 0.95 0.95 2 2 2 10 0.125 2 2 2 2 2 0 2 2 *1 t as t oes t ds t ah t dh t df t vps t vcs t pw t opw t ces t dv t oeh t or t acc t oh *1. corresponding to m pd27c256 symbol. 2. internal address signal is incremented by 1 on rise of 4th x1 input, and is not connected to a pin. test conditions md0 = md1 = v il t m1h + t m1r > C 50 m s in program memory read in program memory read in program memory read in program memory read in program memory read symbol t as t m1s t ds t ah t dh t df t vps t vds t pw t opw t mos t dv t m1h t m1r t pcr t xh , t xl f x t i t m3s t m3h t m3sr t dad t had t m3hr t dfr
25 m pd75p116 program memory write timing program memory read timing t ds t m1h t mis t m3s t pcr t 1 t pw t m1r t ds t oh t dv t df t mos t m3h t as t ah t dh t xl t vds t opw v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 data input data input data output data input t xh t vps t dfr t m3hr t dad t had t xh t xl t dv t pcr t 1 t vds data output data output t m3sr v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 t vps ??
26 m pd75p116 5. package information a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15? 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15? +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
27 m pd75p116 h 64 pin plastic qfp (14 20) p64gf-100-3b8,3be,3br-2 item millimeters inches a b c 23.6?.4 20.0?.2 14.0?.2 0.929?.016 0.795 0.551 d 17.6?.4 0.693?.016 f 1.0 0.039 g 1.0 0.039 h 0.40?.10 0.016 i 0.20 0.008 j 1.0 (t.p.) 0.039 (t.p) k 1.8?.2 0.071 l 0.8?.2 0.031 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 q 0.1?.1 0.004?.004 r 55 55 s 3.0 max. 0.119 max. +0.008 ?.009 +0.009 ?.008 +0.004 ?.005 +0.008 ?.009 +0.009 ?.008 +0.004 ?.003 note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 51 52 32 64 1 20 19 33 i j m n h g f a s p k l m b c d detail of lead end q r +0.10 ?.05
28 m pd75p116 6. recommended soldering conditions the m pd75p116 should be mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document surface mount techno- logy manual (iei-1207). for soldering methods and conditions other than those recommended below, contact our salesman. table 6-1 surface mount type soldering conditions m pd75p116gf-3be : 64-pin plastic qfp (14 20 mm) infrared reflow pin part heating vp15-162-1 ws60-162-1 ir30-162-1 vps recommended condition symbol soldering conditions soldering method package peak temperature: 230 c, duration: 30 sec. max. (at 210 c or above), number of times: once time limit: 2 days * (thereafter 16 hours prebaking required at 125 c) package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: once time limit: 2 days * (thereafter 16 hours prebaking required at 125 c) solder bath temperature: 260 c max., duration: 10 sec. max number of times: once preheating temperature: 120 c max. (package surface temperature), time limit: 2 days * (thereafter 16 hours prebaking required at 125 c) pin part temperature: 300 c max., duration: 3 sec. max. (per device side) wave soldering * for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% 1h. note use of more than one soldering method should be avoided (except in the case of pin part heating). note ensure that the application of (wave soldering) is limited to the lead part and no solder touches the main unit directly . table 6-2 insertion type soldering conditions m pd75p116cw : 64-pin plastic shrink dip (750 mil) h soldering method soldering conditions wave soldering (lead part only) pin part heating solder bath temperature: 260 c max., duration: 10sec. max. pin part temperature: 260 c max., duration: 10sec. max. notice a version of this product with improved recommended soldering conditions is available. for details (improvements such as infrared reflow peak temperature extension (230 c), number of times: twice, relaxation of time limit, etc.), contact nec sales personnel.
29 m pd75p116 appendix a. development tools the following development tools are available for system development using the m pd75p116. hardware in-circuit emulator for 75x series ie-75000-r *1 ie-75001-r ie-75000-r-em *2 ep-75108cw-r ep-75108gf-r ev-9200g-64 pg-1500 emulation board for ie-75000-r and ie-75001-r emulation probe for m pd75p116cw prom programmar this is a prom programmar adapter for m pd75p116cw and connects to pg-1500. this is a prom programmar adapter for m pd75p116gf and connects to pg-1500. emulation probe for m pd75p116gf a 64-pin conversion socket ev-9200g-64 is provided. pa-75p116gf ie control program pg-1500 controller ra75x relocatable assembler software host machine ? pc-9800 series (ms-dos? ver.3.30 to ver.5.00a *3 ) ? ibm pc/at? series (pc dos? ver.3.1) pa-75p108cw *1 maintenance product 2 this is not incorporated in the ie-75001-r. 3 a task swap function is provided with ver.5.00/5.00a; however, a task swap function cannot be used with this software. remarks for development tools manufactured by a third pary, see the 75x series selection guide (if-151) .
30 m pd75p116 document name document no. user's manual instruction application table (i) introductory volume (ii) remote-controlled reception volume (iii) bar-code reader-volume (iv) ic control for msk transmission/reception volume 75x series selection guide application note document name document no. ie-75000-r/ie-75001-r user's manual ie-75000-r-em user's manual ep-75108cw-r user's manual ep-75108gf-r user's manual pg-1500 user's manual operation volume language volume pg-1500 controller user's manual hardware software ra75x assembler package user's manual document name document no. package manual surface mount technology manual quality grade on nec semiconductor devices nec semiconductor device reliability quality control electrostatic discharge (esd) test semiconductor device quality guarantee guide microcomputer related product guide other manufacturer volume note the above related documents may be changed without notice. be sure to use the latest documents for design purposes. h appendix b. related documentation list of device-related documents list of development tool related documents other documents
31 m pd75p116 [memo]
[memo] m pd75p108b no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation.

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